This work addresses the design of efficient arithmetic circuits under strict hardware constraints through the Multiple Constants Multiplication (MCM) problem. While MCM traditionally focuses on implementing multiplications by several integer constants using only additions/subtractions and bit-shifts, existing exact approaches based on ILP, SAT, or CP face scalability issues beyond 10-20 bit constants due to solver precision limits. However, practical applications in signal processing, metrology, and cryptography often require constants of 50 bits and up to several thousand bits. We investigate the Very Large Constant Multiplication (VLCM) problem for a single target constant. Rather than relying on heuristic graph-based methods, we propose a CP-based methodology that optimizes the decomposition of large constants into smaller sub-constants. By identifying bit patterns that reduce the number of required MCM subproblems, the approach aims to minimize the overall computational cost.